Cadence

American River College
Electronics Technology

A member of the Cadence Design Systems University Program .

Cadence Products are used for the following courses:

ET205 -CMOS Mask Design I
Description: This course is an entry level integrated circuit (IC) layout and design in CMOS (Complimentary Metal Oxide Silicon) technology. Practical experience in drawing logic diagrams, transistor level schematics, cross sectional views, STIK diagrams, and in converting STIKS to the actual layout of the layers that will be used to manufacture the EC. The course stresses application of design rules, area estimation, and pin and bus placemen

ET206 -CMOS Mask Design II
Description: CMOS Mask Design II is a continuation of CMOS Mask Design I (ET -96A). This course introduces more complex logic and design rules for integrated circuit layout. This course also includes practical experience in the use of a Unix-based integrated circuit design tool, Cadence VLE, from Cadence Design Systems.

ET-294 - CMOS 3 - Autorouting
Description: This course requires a basic understanding of CMOS transistor layout and functionality. Automated Place and Route (APR) theory and practical applications designing and developing the digital core of a silicon chip are covered. Topics include basic UNIX commands, standard cell transistor layout, net list file syntax, LEF/DEF file syntax, place and route, DRC and LVS verification, embedded blocks, and ECOs.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134